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CY2077FZ ic解密解析
时间:2010-04-26 16:43:52来源:www.pcbsjx.cn 作者:龙人计算机 点击:

  邦凯科技目前主要面向广大客户承接各类IC解密、单片机解密、FPGA解密、DSP解密以及其他专用IC及疑难IC的解密项目,CY2071A是CYPRESS系列单片机之一,目前,邦凯科技在CYPRESS系列单片机解密领域已经取得系列突破,可提供多种型号IC及单片机的解密服务,详情请与邦凯科技联系,这里我们仅提供对CY2071A单片机的基本功能特征介绍:
  芯片解密咨询热线:086-0755-83003639
  E-mail:market2@pcblab.net
  The CY2077 is an EPROM-programmable, high-accuracy,general-purpose, PLL-based design for use in applications such as modems, disk drives, CD-ROM drives, video CD players, DVD players, games, set-top boxes, and data/telecommunications.
  The CY2077 can generate a clock output up to 122 MHz at 5V or 100 MHz at 3.3V. It has been designed to give the customer a very accurate and stable clock frequency with little to zero PPM error. The CY2077 contains a 12-bit feedback counter divider and 10-bit reference counter divider to obtain a very high resolution to meet the needs of stringent design specifications.
  Furthermore, there are eight output divide options of /1, /2, /4, /8, /16, /32, /64, and /128. The output divider can select between the PLL and crystal oscillator output/external clock, providing a total of 16 different options to add more flexibility in designs. TTL or CMOS duty cycles can be selected. Power management with the CY2077 is also very flexible. The user may choose either a PWR_DWN or an OE feature with which both have integrated pull-up resistors. PWR_DWN and OE signals can be programmed to have asynchronous and synchronous timing with respect to the output signal. There is a weak pull-down on the output that will pull CLKOUT LOW when either the PWR_DWN or OE signal is active. This weak pull-down can easily be overridden by another clock signal in designs where multiple clock signals share a signal path.Multiple options for output selection, better power distribution layout, and controlled rise and fall times enable the CY2077 to be used in applications that require low jitter and accurate reference frequencies.

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