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AT89C51CC03C芯片解密
时间:2010-04-02 16:47:09来源:www.pcbsjx.cn 作者:龙人计算机 点击:

  邦凯科技长期提供MICROCHIP单片机、SYNCMOS单片机、ALTERA单片机、ATMEL单片机、VERSACHIPS单片机、HITACHI单片机、NXP单片机、EMC单片机、DALLAS单片机、INTEL单片机、ZILOG单片机、XILINX单片机、WINBOND单片机、Freescale单片机、STC单片机、SST单片机、LATTICE单片机等近五十个系列单片机解密服务。
  我们经过多年的研究,对单片机的算法、架构和工艺进行了深入的研究,精心设计的解密技术流程在确保解密芯片绝对安全的同时,也把芯片解密的周期降到最低,极大的保证了客户在解密过程中的工程控制和经济效益。
  AT89C51CC03C等ATMEL系列单片机解密是邦凯科技早期就率先突破的单片机解密类型之一,经过多年的反复实验,目前我们的解密技术已经相当成熟,可提供高质量、高可靠性的解密服务。
  有AT89C51CC03C解密需求者,请直接与我们联系:
  24小时服务热线:086-0755-83003639
  E-mail:
market2@pcblab.net
  AT89C51CC03C Features:
  80C51 Core Architecture
  256 Bytes of On-chip RAM
  2048 Bytes of On-chip ERAM
  64K Bytes of On-chip Flash Memory
  – Data Retention: 10 Years at 85°C
  – Read/Write Cycle: 100K
  2K Bytes of On-chip Flash for Bootloader
  2K Bytes of On-chip EEPROM
  Read/Write Cycle: 100K
  Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply
  14-sources 4-level Interrupts
  Three 16-bit Timers/Counters
  Full Duplex UART Compatible 80C51
  High-speed Architecture
  – In Standard Mode:
  40 MHz (Vcc 3V to 5.5V, both Internal and external code execution)
  60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
  – In X2 mode (6 Clocks/machine cycle)
  20 MHz (Vcc 3V to 5.5V, both Internal and external code execution)
  30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
  Five Ports: 32 + 4 Digital I/O Lines
  Five-channel 16-bit PCA with
  – PWM (8-bit)
  – High-speed Output
  – Timer and Edge Capture
  Double Data Pointer
  21-bit WatchDog Timer (7 Programmable Bits)
  A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
  SPI Interface, (PLCC52, VPFP64 and CABGA 64 packages only)
  Full CAN Controller
  – Fully Compliant with CAN Rev 2.0A and 2.0B
  – Optimized Structure for Communication Management (Via SFR)
  – 15 Independent Message Objects
  – Each Message Object Programmable on Transmission or Reception
  – Individual Tag and Mask Filters up to 29-bit Identifier/Channel
  – 8-byte Cyclic Data Register (FIFO)/Message Object
  – 16-bit Status and Control Register/Message Object
  – 16-bit Time-Stamping Register/Message Object
  – CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
  Object
  – Access to Message Object Control and Data Registers Via SFR
  – Programmable Reception Buffer Length Up To 15 Message Objects
  – Priority Management of Reception of Hits on Several Message Objects at the
  Same Time (Basic CAN Feature)
  – Priority Management for Transmission
  – Message Object Overrun Interrupt
  – Supports
  – Time Triggered Communication
  – Autobaud and Listening Mode
  – Programmable Automatic Reply Mode
  – 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode
  – Readable Error Counters
  – Programmable Link to On-chip Timer for Time Stamping and Network
  Synchronization
  – Independent Baud Rate Prescaler
  – Data, Remote, Error and Overload Frame Handling

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